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  rev. 1.10 1 march 10, 2005 ht36b2 8-bit music synthesizer mcu block diagram features  operating voltage: 3.6v~5.0v  operating frequency: 3.58mhz~12mhz (typ. 11.059mhz)  32 bidirectional i/o lines  two 16-bit programmable timer/event counters with overflow interrupts  watchdog timer  built-in 8-bit mcu with 576  8 bits ram  built-in 128k  16-bit rom for program/data shared  two high d/a converter resolution: 16 bits  polyphonic up to 16 notes  independent pan and volume mix can be assigned to each sound component  sampling rate of 44.1khz as 11.059mhz for system frequency  eight-level subroutine nesting  halt function and wake-up feature reduce power consumption  bit manipulation instructions  16-bit table read instructions  63 powerful instructions  all instructions in 1 or 2 machine cycles  28-pin sop, 56-pin ssop package general description the ht36b2 is an 8-bit high performance risc archi - tecture microcontroller specifically designed for various music applications. it provides an 8-bit mcu and a 16 channel wavetable synthesizer. the program rom which can be easily programmed is composed of both program control codes and wavetable voice codes. the ht36b2 has a built-in 8-bit microprocessor which programs the synthesizer to generate the melody by setting the special register from 20h~2ah. a halt fea - ture is provided to reduce power consumption.        
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pad assignment chip size: 2975  3550 (  m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht36b2 rev. 1.10 3 march 10, 2005               
                 
            
             
       
               
                         
             
                         
pad coordinates unit:  m pad no. x y pad no. x y 1  1327.608 1607.250 22 1320.992  146.680 2  1321.808  1607.630 23 1320.992  46.680 3  1221.808  1607.630 24 1320.992 63.920 4  1111.208  1607.630 25 1320.992 163.920 5  1011.208  1607.630 26 1320.992 274.520 6  900.608  1607.630 27 1320.992 374.520 7  800.608  1607.630 28 1320.992 485.120 8  690.008  1607.630 29 1324.492 1571.300 9  590.008  1607.630 30 1211.492 1571.300 10  479.408  1607.630 31 1099.052 1571.300 11  379.408  1607.630 32 950.392 1571.300 12  268.808  1607.630 33 833.168 1571.200 13  168.808  1607.630 34 155.316 1571.200 14  58.208  1607.630 35 34.192 1604.750 15 41.792  1607.630 36  572.908 1604.750 16 152.392  1607.630 37  694.032 1607.250 17 252.392  1607.630 38  795.808 1607.250 18 362.992  1607.630 39  906.408 1607.250 19 462.992  1607.630 40  1006.408 1607.250 20 571.392  1607.630 41  1117.008 1607.250 21 1320.992  257.280 42  1217.008 1607.250 pad description pad name i/o internal connection function pa0~pa7 i/o pull-high or none bidirectional 8-bit input/output port, wake-up by mask option pb0~pb7 i/o pull-high or none bidirectional 8-bit input/output port pc0~pc7 i/o pull-high or none bidirectional 8-bit input/output port pd0~pd7 i/o pull-high or none bidirectional 8-bit input/output port int i pull-high external interrupt rch o  r channel audio output lch o  l channel audio output vdda  dac power supply vssa  negative power supply of dac, ground osc1 osc2 i o  osc1 and osc2 are connected to an rc network or a crystal (by mask op - tion) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/8 system clock. the system clock may come from the crystal, the two pins cannot be floating. vss  negative power supply, ground vdd  positive power supply res i  reset input, active low ht36b2 rev. 1.10 4 march 10, 2005
absolute maximum ratings supply voltage .............................v ss  0.3v to v ss +6v storage temperature ...........................  50  cto125  c input voltage .............................v ss  0 . 3v to v dd +0.3v operating temperature ..........................  25  cto70  c note: these are stress ratings only. stresses exceeding the range specified under  absolute maximum ratings  may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage  3.6 4.5 5.5 v i dd operating current 4.5v no load, f osc =11.0592mhz  16 32 ma i stb standby current (wdt disabled) 4.5v no load, system halt  13  a i oh i/o ports source current 4.5v v oh =4.5v 5  ma i ol i/o ports sink current 4.5v v ol =0.5v 5  ma v ih input high voltage for i/o ports 4.5v  0.8v dd  v dd v v il input low voltage for i/o ports 4.5v  0  0.2v dd v r ph pull-high resistance of i/o ports (int ) 4.5v v il =0v  30  k  a.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions mcu interface f osc system frequency 5v 11.059mhz crystal  11.059  mhz f sys system clock 5v  8  12 mhz t wdt watchdog time-out period (rc)  without wdt prescaler 9 17 35 ms t res external reset low pulse width  1  s symbol parameter figure min. typ. max. unit dac interface f bc dck bit clock frequency fig 1  f sys /16  mhz t ch dck bit clock h level time fig 1 600  ns t dos data output setup time fig 1 200  ns t doh data output hold time fig 1 200  ns t lcs load clock setup time fig 1 200  ns t lch load clock hold time fig 1 200  ns ht36b2 rev. 1.10 5 march 10, 2005
ht36b2 rev. 1.10 6 march 10, 2005 function description execution flow the system clock for the ht36b2 is derived from either a crystal or an rc oscillator. the oscillator frequency di - vided by 2 is the system clock for the mcu and it is inter - nally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in one cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter  pc the 13-bit program counter (pc) controls the sequence in which the instructions stored in program rom are ex - ecuted and its contents specify a maximum of 8192 ad - dresses for each bank. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to retrieve the proper instruction. other - wise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. once a control transfer takes place, an additional dummy cycle is required. * *
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1   execution flow mode program counter *16 *15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset pf3 pf2 pf1 pf0 0000000000000 timer/event counter 0 overflow pf3 pf2 pf1 pf0 0000000001000 timer/event counter 1 overflow pf3 pf2 pf1 pf0 0000000001100 skip program counter+2 loading pcl pf3 pf2 pf1 pf0 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch pf3 pf2 pf1 pf0 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine pf3 pf2 pf1 pf0 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: bits of program counter @7~@0: bits of pcl #12~#0: bits of instruction code s12~s0: bits of stack register @7~@0: bits of pcl pf3~pf0: bits of bank register
ht36b2 rev. 1.10 7 march 10, 2005 program rom ht36b2 provides 17 address lines w a16~0 to read the program rom which is up to 2m bits, and is comm only used for the wavetable voice codes and the program memory. it provides two address types, one type is for program rom, which is addressed by a bank pointer pf3~0 and a 13-bit program counter pc 12~0; and the other type is for wavetable code, which is addressed by the start address st15~0. on the program type, wa16~0= pf3~0  2 13 + pc12~0. on the wavetable rom type, wa16~0=st15~0  2 5 . program memory  rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 8192  16 bits, addressed by the bank pointer, program counter and table pointer. certain locations in the program memory of each bank are reserved for special usage:  location 000h on bank0 this area is reserved for the initialization program. af - ter a chip reset, the program always begins execution at location 000h on bank0.  location 008h this area is reserved for the timer/event counter 0 in- terrupt service program on each bank. if timer interrupt results from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008h corresponding to its bank.  location 00ch this area is reserved for the timer/event counter 1 interrupt service program on each bank. if a timer in - terrupt results from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00ch corre - sponding to its bank.  table location any location in the rom space can be used as look-up tables. the instructions tabrdc [m] (the cur - rent page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the tblh. the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), which indicates the table lo - cation. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruc - tion, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in this case, using the ta- ble read instruction in the main routine and the isr si- multaneously should be avoided. however, if the table read instruction has to be applied in both the main rou- tine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related in- structions need two cycles to complete the operation. these areas may function as normal program mem - ory depending upon user requirements.  bank pointer the program memory is organized into 16 banks and each bank into 8192  16 bits of program rom. pf3~0 is used as the rom bank pointer. after an instruction has been executed to write data to the pf register to select a different bank, note that the new bank will not be selected immediately. it is not until the following in - struction has completed execution that the bank will be actually selected. instruction(s) table location *16 *15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p16 p15 p14 p13 p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] p16 p15 p14 p13 11111@7@6@5@4@3@2@1@0 table location note: *12~*0: table location bits @7~@0: table pointer bits p12~p8: current program counter bits p16~p13: bits of bank pf3~pf0     &     & *  7     :    .  $      .  .          .    $        $ ;   7    .    ' $ $ 8    .     . /
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ht36b2 rev. 1.10 8 march 10, 2005 wavetable rom the st15~0 is used to defined the start address of each sample on the wavetable and read the waveform data from the location. ht36b2 provides 21 output address lines from wa16~0, the st15~0 is used to locate the major 16 bits of 21 lines and the undefined data from wa4~0 is always set to 00000b. so the start address of each sample have to be located at a multiple of 32 bytes. otherwise, the sample will not be read out cor - rectly because it has a wrong starting code. stack register  stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge, the con - tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig - naled by a return instruction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be ser- viced. this feature prevents stack overflow allowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is subsequently exe- cuted, a stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). data memory  ram the data memory is designed with 3  256  8 bits. the data memory is divided into three functional groups: special function registers, wavetable function register, and general purpose data memory (3  192  8). most of them are read/write, but some are read only. the special function registers include the indirect ad - dressing register 0/1 (00h/02h), the memory pointer register (mp0;02h, mp1;04h), the ram address bank pointer (bp;01h), the 8-bit mcu accumulator ( acc ;05h), the program counter lower-byte register (pcl;06h), the table pointer (tblp;07h), the table higher-order byte register (tblh;08h), the watchdog timer option setting register (wdts;09h), the status register (status;0ah), the interrupt control register (intc;0bh), the timer/event counter 0 higher-order byte register (tmr0h;0ch), the timer/event counter 0 lower-order byte register (tmr0l;0dh), the timer/event counter 0 control register (tmr0c;0eh), the timer/event counter 1 higher-order byte register (tmr1h;0fh), the timer/event counter 1 lower-order byte register (tmr1l;10h), the timer/event counter 1 control register (tmr1c;11h), the i/o registers (pa;12h, pb;14h, pc;16h, pd;18h), the program rom bank select (pf;1ch)), the d/a converter (dah;1dh, dal;1eh, dac;1fh) and the i/o control registers (pac;13h, pbc;15h, pcc;17h, pdc;19h). the wavetable function register is defined between 20h~2ah. the remaining space before the 40h is re - served for future expansion usage and reading these lo -   &  & 
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ht36b2 rev. 1.10 9 march 10, 2005 cations will return the result 00h. the general purpose data memory, addressed from 40h to ffh, is used for data and control information under instruc tion command. all data memory areas can handle arithmetic, logic, in - crement, decrement and rotate operations directly. ex - cept for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instructions, respectively. they are also indirectly accessible through memory pointer registers (mp0;01h, mp1;03h) and bp. indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] access data memory pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h directly will return the result 00h. and writing directly results in no operation. the function of data movement between two indirect ad - dressing registers, is not supported. the memory pointer registers, mp0 (for bank0 only) and mp1, are 8-bit register which can be used to access the data memory by combining corresponding indirect address - ing registers. accumulator the accumulator closely relates to alu operations. it is mapped to location 05h of the data memory and it can operate with immediate data. the data movement be- tween two data memory locations must pass through the accumulator. arithmetic and logic unit  alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions:  arithmetic operations (add, adc, sub, sbc, daa)  logic operations (and, or, xor, cpl)  rotation (rl, rr, rlc, rrc)  increment & decrement (inc, dec)  branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but can also change the status register. status register  status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf) and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and program counters, bits in the status register can be altered by instructions like any other register. any data written into the status regis - ter will not change the to or program counters. in addi - tion it should be noted that operations related to the status register may give different results from those in - tended. the to and pdf flags can only be changed by system power up, watchdog timer overflow, executing the halt instruction and clearing the watchdog timer. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of status are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. interrupt the ht36b2 provides one external interrupt, and two in- ternal timer/event counter interrupts on each bank. the interrupt control register (intc;0bh) contains the inter - rupt control bits that sets the enable/disable and the in - terrupt request flags. bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise c is cleared. it is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logical operation is zero, otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the high - est-order bit, or vice versa, otherwise ov is cleared. 4 pdf pdf is cleared by either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7  unused bit, read as  0  status (0ah) register
ht36b2 rev. 1.10 10 march 10, 2005 once an interrupt subroutine is serviced, all other inter - rupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt needs servicing within the service routine, the pro - grammer may set the emi bit and the corresponding bit of the intc to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the sp is decre - mented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupt have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at specified locations in the program memory. only the program counter is pushed onto the stack. if the contents of the register and status register (status) are altered by the interrupt service program which may corrupt the desired control se - quence, then the programmer must save the contents first. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (t0f;bit 5 of the intc), caused by a timer/event counter 0 overflow. when the interrupt is enabled, and the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related in- terrupt request flag (t0f) will be reset and the emi bit cleared to disable further interrupts. the timer/event counter 1 interrupt is operated in the same manner as timer/event counter 0. the related in- terrupt control bits et1i and t1f of the timer/event counter 1 are bit 3 and bit 6 of the intc respectively. external interrupt is initialized by setting the external re - quest flag (eei; bit 1 of the intc), caused by a high-to low voltage pulse from the int pad. when the interrupt is enabled, and the stack is not full and the eei bit is set, a subroutine call to location 04h will occur. the related interrupt request flag (eif) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, the ret or reti in - struction may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the priorities in the following table apply. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch the timer/event counter 0/1 interrupt request flag (t0f/t1f), enable timer/event counter 0/1 bit (et0i/et1i), enable master interrupt bit (emi) consti - tute an interrupt control register (intc) which is located at 0bh in the data memory. emi, et0i, et1i are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (t0f, t1f) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the  call subroutine  within the interrupt subroutine. be - cause interrupts often occur in an unpredictable manner or need to be serviced immediately in some applica - tions, if only one stack is left and enabling the interrupt is not well controlled, once the  call subroutine  operates in the interrupt subroutine, it may damage the original control sequence. oscillator configuration the ht36b2 provides two types of oscillator circuit for the system clock, i.e., rc oscillator and crystal oscilla- tor. no matter what type of oscillator, the signal divided by 2 is used for the system clock. the halt mode stops the system oscillator and ignores external signal to con- serve power. if the rc oscillator is used, an external re- sistor between osc1 and vss is required, and the range of the resistance should be from 30k  to 680k  . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to synchronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscilla - tion may vary with vdd, temperature, and the chip itself due to process variations. it is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. on the other hand, if the crystal oscillator is selected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two ex -   6     .   3      $    .   3      $   "   " 
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9 " d "    "  % ! ! system oscillator
ht36b2 rev. 1.10 11 march 10, 2005 ternal capacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 78  s. the wdt oscillator can be disabled by mask option to conserve power. watchdog timer  wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (mcu system clock divided by 4), determined by mask op- tions. this timer is designed to prevent a software mal- function or sequence jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by mask option. if the watchdog timer is dis- abled, all the executions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 78  s normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of ap - proximately 20ms. this time-out period may vary with temperature, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be real - ized. writing data to ws2, ws1, ws0 (bits 2, 1, 0 of the wdts) can give different time-out periods. if ws2, ws1, ws0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. the high nibble and bit 3 of the wdts are reserved for user defined flags, and the programmer may use these flags to indicate some specified status. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize a  chip reset  and set the status bit to. whereas in the halt mode, the overflow will initialize a  warm reset  wherein only the program counter and sp are reset to zero. to clear the wdt contents (including the wdt prescaler ), three methods are implemented, namely, external reset (a low level to res ), software instruc - tions, or a halt instruction. the software instructions include clr wdt and the other set  clr wdt1 and bit no. label function 0 emi controls the master (global) interrupt (1=enable; 0=disable) 1 eei controls the external interrupt (1=enable; 0=disable) 2 et0i controls the timer/event counter 0 interrupt (1=enable; 0=disable) 3 et1i controls the timer/event counter 1 interrupt (1=enable; 0=disable) 4 eif external interrupt (int pad) request flag 5 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 6 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) 7  unused bit, read as  0  intc (0bh) register " 6    7 .   $ 3 8       .  $      a ! * .     3         .  $         $  .   e a ! * . *  7   $   a "  a "
   8     $  "    3  a ! *  "  watchdog timer
ht36b2 rev. 1.10 12 march 10, 2005 clr wdt2. of these two types of instructions, only one can be active depending on the mask option  clr wdt times selection option  .ifthe  clr wdt  is se - lected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case  clr wdt1  and  clr wdt2  are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt, otherwise, the wdt may reset the chip due to time-out. power down operation  halt the halt mode is initialize by a halt instruction and results in the following:  the system oscillator will turn off but the wdt oscilla - tor keeps running (if the wdt oscillator is selected). watchdog timer  wdt  the contents of the on-chip ram and registers remain unchanged.  the wdt and wdt prescaler will be cleared and starts to count again (if the clock comes from the wdt oscillator).  all i/o ports maintain their original status.  the pdf flag is set and the to flag is cleared.  the halt pin will output a high level signal to disable the external rom. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig- nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per- forms a  warm reset  . by examining the to and pdf flags, the cause for a chip reset can be determined. the pdf flag is cleared when there is a system power-up or by executing the clr wdt instruction and it is set when a halt instruction is executed. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp, the others remain in their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by mask option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. if awakening from an interrupt, two se - quences may occur. if the related interrupts is disabled or the interrupts is enabled but the stack is full, the pro - gram will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, a regular in - terrupt response takes place. once a wake-up event occurs, it takes 1024 t sys (sys - tem clock period) to resume to normal operation. in other words, a dummy cycle period will be inserted after the wake-up. if the wake-up results from an interrupt ac - knowledge, the actual interrupt subroutine will be de - layed by one more cycle. if the wake-up results in next instruction execution, this will be executed immediately after a dummy period has finished. if an interrupt re - quest flag is set to  1  before entering the halt mode, the wake-up function of the related interrupt will be dis - abled. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur:  res reset during normal operation  res reset during halt  wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a  warm re - set  that just resets the program counter and sp, leaving the other circuits in their original state. some registers remain unchanged during other reset conditions. most registers are reset to the  initial condition  when the re - set conditions are met. by examining the pdf and to flags, the program can distinguish between different  chip resets  .  " " *  # " % ! ! " " * . *  7   $       .      reset timing chart  # " % ! ! reset circuit a ! * &  ' * a ! * *  7   $         # "  $  =      a   7 .       $ <    $  . !    3    ; " " *      ;        .  $       "  ( reset configuration
ht36b2 rev. 1.10 13 march 10, 2005 the registers status is summarized in the following table: register reset (power on) res reset (normal operation) res reset (halt) wdt time-out (normal operation) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --uu uuuu --01 uuuu --1u uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pf ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu dal xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu dac ---- -000 ---- -000 ---- -000 ---- -000 ---- -uuu chan 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu freqnh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu freqnl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu addrh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu addrl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu reh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rel xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu env xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu lvc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rvc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu note:  *  stands for warm reset  u  stands for unchanged  x  stands for unknown  -  stands for unimplemented
ht36b2 rev. 1.10 14 march 10, 2005 to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note:  u  stands for  unchanged  to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra delay of 1024 system clock pulses during system power up or when the system awakes from a halt state. when a system power-up occurs, the sst delay is added during the reset period. but when the reset co - mes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. the functional units chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after a master reset, wdt begins counting timer/event counter (0/1) off input/output ports input mode sp points to the top of the stack timer/event counter two timer/event counters are implemented in the ht36b2. the timer/event counter 0 and timer/event counter 1 contain 16-bit programmable count-up coun - ters and the clock comes from the system clock divided by 4. there are three registers related to timer/event coun - ter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh). writing tmr0l only writes the data into a low byte buffer, and writing tmr0h will write the data and the contents of the low byte buffer into the timer/event counter 0 preload register (16-bit) simultaneously. the timer/event counter 0 preload register is changed by writing tmr0h operations and writing tmr0l will keep the timer/event counter 0 preload register unchanged. reading tmr0h will also latch the tmr0l into the low byte buffer to avoid a false timing problem. reading tmr0l returns the contents of the low byte buffer. in other words, the low byte of the timer/event counter 0 cannot be read directly. it must read the tmr0h first to make the low byte contents of the timer/event counter 0 latched into the buffer. there are three registers related to the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). the timer/event counter 1 operates in the same man - ner as timer/event counter 0. the tmr0c is the timer/event counter 0 control regis - ter, which defines the timer/event counter 0 options. the timer/event counter 1 has the same options with timer/event counter 0 and is defined by tmr1c. the timer/event counter control registers define the operating mode, counting enable or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr) pin. the timer mode functions as a normal timer with the clock source coming from the instruction clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr). the counting is based on the instruction clock. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter preload register and simulta - neously generates the corresponding interrupt request flag (t0f/t1f; bit 5/6 of the intc). bit no. label function 0~2  unused bit, read as  0  3te defines the tmr active edge of timer/event counter 0 (0=active on low to high; 1=active on high to low) 4 ton enable/disable timer counting (0=disable; 1=enable) 5  unused bit, read as  0  6 7 tm0 tm1 defines the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c/tmr1c register
ht36b2 rev. 1.10 15 march 10, 2005 in pulse width measurement mode with the ton and te bits equal to one, once the tmr has received a transient from low to high (or high to low; if the te bit is 0) it will start counting until the tmr returns to the original level and resets the ton. the measured result will remain in the register even if the activated transient occurs again. in other words, only one cycle measurements can be done. until setting the ton, the cycle measurement will function again as long as it receives further transient pulse. note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter and the preload register issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of the tmr0c/tmr1c) should be set to 1. in the pulse width measurement mode, the ton will be cleared automatically after the measurement cycle is completed. but in the other two modes the ton can only be reset by instruction. the overflow of the timer/ event counter is one of the wake-up sources. no matter what the operation mode is, writing a  0  to et0i/et1i can disable the corresponding interrupt service. in the case of timer/event counter off condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs. when the timer/event counter (reading tmr0h/tmr1h) is read, the clock will be blocked to avoid errors. as this may results in a counting error, this must be taken into consideration by the programmer. the two timer counters of the ht36b2 are internal clock mode only, so only timer mode can be selected. there - fore the (tm1, tm0) bits can only be set to (tm1,tm0) = (1,0), and the other clock modes are invalid. input/output ports there are 32 bidirectional input/output lines labeled from pa to pd, which are mapped to the data memory of [12h], [14h], [16h], [18h] respectively. all these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h or 18h). for output oper - ation, all data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc) to control the input/output configuration. with this control register, cmos output or schmitt trig - f !  " f f !  " f   e !    .    a     .  $    $  .   ;          .         = .  $    $  .   ;      a     . (      = . (   " 6    7 . a  8     . /   . $   6 1 a   8                       8 .     $     8 .     $         !   ! , % ! ! % ! ! input/output ports " 6    7 .   $ 3 8   *  *   * # *  *   *  )      . a  =          7     $ =  .  $    $  *  7     :    .  $      .      $  = .   ;      *  7     :     $      .  !    .       $  =  :   9  $ < * $ . (         ' $ < .  6     9 9    ) ! timer/event counter 0/1
ht36b2 rev. 1.10 16 march 10, 2005 ger input with or without pull-high resistor (mask option) structures can be reconfigured dynamically under soft - ware control. to function as an input, the corresponding latch of the control register must write a  1  . the pull-high resistance will be exhibited automatically if the pull-high option is selected. the input source also de - pends on the control register. if the control register bit is  1  , input will read the pad state. if the control register bit is  0  , the contents of the latches will move to the internal bus. the latter is possible in  read-modify-write  instruc - tion. for output function, cmos is the only configura - tion. these control registers are mapped to locations 13h, 15h, 17h and 19h). after a chip reset, these input/output lines remain at high levels or floating (mask option). each bit of these in - put/output latches can be set or cleared by the set [m].i or clr [m].i (m=12h, 14h, 16h or 18h) instruction. some instructions first input data and then follow the output operations. for example, the set [m].i, clr [m].i, cpl [m] and cpla [m] instructions read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability to wake-up the de - vice. 16 channel wavetable synthesizer wavetable function memory mapping special register for wavetable synthesizer ram b7 b6 b5 b4 b3 b2 b1 b0 20h vm fr  ch3 ch2 ch1 ch0 21h bl3 bl2 bl1 bl0 fr11 fr10 fr9 fr8 22h fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 23h st15 st14 st13 st12 st11 st10 st9 st8 24h st7 st6 st5 st4 st3 st2 st1 st0 25h wbs re14 re13 re12 re11 re10 re9 re8 26h re7 re6 re5 re4 re3 re2 re1 re0 27h a_r  vl9 vl8 env1 env0 vr9 vr8 29h vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 2ah vr7 vr6 vr5 vr4 vr3 vr2 vr1 vr0 wavetable function register table register name register function b7 b6 b5 b4 b3 b2 b1 b0 20h channel number selection ch3 ch2 ch1 ch0 20h change parameter selection vm fr 21h block number selection bl3 bl2 bl1 bl0 21h frequency number selection fr11 fr10 fr9 fr8 22h fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 23h start address selection st15 st14 st13 st12 st11 st10 st9 st8 24h st7 st6 st5 st4 st3 st2 st1 st0 25h waveform format selection wbs 25h repeat number selection re14 re13 re12 re11 re10 re9 re8 26h re7 re6 re5 re4 re3 re2 re1 re0 27h envelope type selection env1 env0 27h attach and release selection a_r 27h left volume controller vl9 vl8 29h vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 27h right volume controller vr9 vr8 2ah vr7 vr6 vr5 vr4 vr3 vr2 vr1 vr0
ht36b2 rev. 1.10 17 march 10, 2005  ch3~0 channel number selection the ht36b2 has a built-in 16 output channels and ch3~0 is used to define which channel is selected. when this register is written to, the wavetable synthe - sizer will automatically output the dedicated pcm code. so this register is also used as a start playing key and it has to be written to after all the other wavetable function registers are already defined.  change parameter selection these two bits, vm and fr, are used to define which register will be updated on this selected channel. there are two modes that can be selected to reduce the process of setting the register. refer to the follow - ing table: vm fr function 0 0 update all the parameter 0 1 only update the frequency number 1 0 only update the volume  output frequency definition the data on bl3~0 and fr11~0 are used to define the output speed of the pcm file, i.e. it can be used to generate the tone scale. when the fr11~0 is 800h and bl3~0 is 6h, each sample data of the pcm code will be sent out sequentially. when the f osc is 12.8mhz, the formula of a tone fre- quency is: f out =f record  50khz sr  fr11 ~ 0 2 (17 bl3~0) - where f out is the output signal frequency, f record and sr is the frequency and sampling rate on the sample code, respectively. so if a voice code of c3 has been recorded which has the f record of 261hz and the sr of 11025hz, the tone frequency (f out ) of g3: f out =196hz. can be obtained by using the formula: 196hz= 261hz  50khz 11025hz  fr11 ~ 0 2 (17 bl3~0) - a pair of the values fr11~0 and bl3~0 can be deter - mined when the f osc is 12.8mhz.  start address definition the ht36b2 provides two address types for extended use, one is the program rom address which is pro - gram counter corresponding with pf value, the other is the start address of the pcm code. the st15~0 is used to define the start address of each pcm code and reads the waveform data from this location. the ht36b2 provides 16 input data lines from wa15~0, the st15~0 is used to locate the major 16 bits i.e. wa15~5 and the undefined data from wa4~0 is always set as 00000b. in other words, the wa15~0=st15~0  2 5 . so each pcm code has to be located at a multiple of 32. otherwise, the pcm code will not be read out correctly because it has a wrong start code.  waveform format definition the ht36b2 accepts two waveform formats to ensure a more economical data space. wbs is used to define the sample format of each pcm code. wbs=0 means the sample format is 8-bit wbs=1 means the sample format is 12-bit the 12-bit sample format allocates location to each sample data. refer to the waveform format statement as shown below.  repeat number definition the repeat number is used to define the address which is the repeat point of the sample. when the re - peat number is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80h) until the volume becomes close. the re14~0 is used to calculate the repeat address of the pcm code. the process for setting the re14~0 is to write the 2
s complement of the repeat length to re14~0, with the highest carry ignored. the ht36b2 will retrieve the repeat address by adding the re14~0 to the address of the end code, then jump to the ad- dress to repeat this range.  left and right volume control the ht36b2 provides the left and right volume control independently. the left and right volume are con - trolled by vl9~0 and vr9~0 respectively. the chip provides 1024 levels of controllable volume, the 000h is the maximum and 3ffh is the minimum output vol - ume.  envelope type definition the ht36b2 provides a function to easily program the envelope by setting the data of env1~0 and a_r. it forms a vibrato effect by a change of the volume to at - tach and release alternately. the a_r signal is used to define the volume change in attach mode or release mode and env1~0 is used to define which volume control bit will be changeable. on the attach mode, the control bits will be sequen - tially signaled down to  0  . on the release mode, the control bits will be sequentially signaled up to  1  . the relationship is shown in the following table. 
 ,  +         &  '
'
&
 , & ,   .   7     ; . =    . 3 $ =  g .  . 7     . $   . =    . 6   ?     
    , ' ) $   > c & c . &  ;  . )    c  c .   = =   . )    c ' c . ' $ < . )     .   7     ; . =    . 3 $ =  waveform format
ht36b2 rev. 1.10 18 march 10, 2005 a_r env1 env0 volume control bit control bit final value mode 0 0 0 vl2~0, vr2~0 111b release mode 0 0 1 vl1~0, vr1~0 11b 0 1 0 vl0, vr0 1b x 1 1 no bit unchanged no change mode 1 0 0 vl2~0, vr2~0 000b attach mode 1 0 1 vl1~0, vr1~0 00b 1 1 0 vl0, vr0 0b envelope type definition  the pcm code definition the ht36b2 can provide the voice format of the signed 8-bit raw pcm. and the mcu will take the voice code 80h as the end code. so each pcm code section must be ended with the end code 80h. digital to analog converter (dac) the ht36b2 provides two 16-bit current type dac de - vice controlled by the mcu or wavetable synthesizer for driving the external speaker through an external npn transistor. it is in fact an optional object used for the wavetable synthesizer dac or general dac, this is cho- sen by mask option and dac control register. if general dac is chosen for application, then the wavetable synthesizer is disabled because the dac is taken up and controlled by the mcu. if general dac is selected, the programmer must write the voice data to register the dal and dah to get the corresponding analog data. for mask option enable dac register and enable selwl and selwr, then the table becomes useful. bit no. label function 0 selwr selwr=1: right channel dac data from wavetable selwr=0: right c0hannel dac data from mcu (default) 1 daon daon=1: dac on daon=0: dac off (default) 2 selwl selwl=1: left channel dac data from wavetable selwl=0: left channel dac data from mcu (default) 3~7  unused bit, read as  0  dac (1fh) control register mask option no. mask option function 1 wdt source on-chip rc/instruction clock/ disable wdt 2 clrwdt times one time, two times (clr wdt1/wdt2) 3 wake-up pa only 4 pull-high pa, pb, pc, pd input 5 osc mode crystal or resistor type 6 lvr/lvd low voltage detection
application circuits ht36b2 rev. 1.10 19 march 10, 2005   &         & % ! ! +   2  ?  2 %   9   2 ( ) % ! !         % " "  #   * . )   * .  "   
 8  '  &
,   +                     !   !  % ! ! +   2  ?  2 %   9   2 ( ) % ! !         % " "  #   * . )   * .  "   
 8 
,   +  % ! ! "    8                         !   !  '  & % ! ! "    8      % " "  % " " % " "  % " " % ! ! % ! ! % ! !    +   2  ?  2 % ! ! % ! ! % ! !    +   2  ?  2        "   " 
?   -  & @  # "   8   ?  2 % ! !  # "  "  % ! !   8   ?  2
instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht36b2 rev. 1.10 20 march 10, 2005
mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address  : flag is affected  : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. ht36b2 rev. 1.10 21 march 10, 2005
instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc  acc+[m]+c affected flag(s) to pdf ov z ac c  adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m]  acc+[m]+c affected flag(s) to pdf ov z ac c  add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc  acc+[m] affected flag(s) to pdf ov z ac c  add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc  acc+x affected flag(s) to pdf ov z ac c  addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m]  acc+[m] affected flag(s) to pdf ov z ac c  ht36b2 rev. 1.10 22 march 10, 2005
and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc  acc  and  [m] affected flag(s) to pdf ov z ac c    and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc  acc  and  x affected flag(s) to pdf ov z ac c    andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m]  acc  and  [m] affected flag(s) to pdf ov z ac c    call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack  pc+1 pc  addr affected flag(s) to pdf ov z ac c   clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m]  00h affected flag(s) to pdf ov z ac c  ht36b2 rev. 1.10 23 march 10, 2005
clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i  0 affected flag(s) to pdf ov z ac c  clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt  00h pdf and to  0 affected flag(s) to pdf ov z ac c 00  clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt  00h* pdf and to  0* affected flag(s) to pdf ov z ac c 0* 0*  clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt  00h* pdf and to  0* affected flag(s) to pdf ov z ac c 0* 0*  cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1  s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m]  [m ] affected flag(s) to pdf ov z ac c    ht36b2 rev. 1.10 24 march 10, 2005
cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1  s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc  [m ] affected flag(s) to pdf ov z ac c    daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0  (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0  (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4  acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4  acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c   dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m]  [m]  1 affected flag(s) to pdf ov z ac c    deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc  [m]  1 affected flag(s) to pdf ov z ac c    ht36b2 rev. 1.10 25 march 10, 2005
halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation pc  pc+1 pdf  1 to  0 affected flag(s) to pdf ov z ac c 01  inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m]  [m]+1 affected flag(s) to pdf ov z ac c    inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc  [m]+1 affected flag(s) to pdf ov z ac c    jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc  addr affected flag(s) to pdf ov z ac c  mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc  [m] affected flag(s) to pdf ov z ac c  ht36b2 rev. 1.10 26 march 10, 2005
mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc  x affected flag(s) to pdf ov z ac c  mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m]  acc affected flag(s) to pdf ov z ac c  nop no operation description no operation is performed. execution continues with the next instruction. operation pc  pc+1 affected flag(s) to pdf ov z ac c  or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc  acc  or  [m] affected flag(s) to pdf ov z ac c    or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc  acc  or  x affected flag(s) to pdf ov z ac c    orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m]  acc  or  [m] affected flag(s) to pdf ov z ac c    ht36b2 rev. 1.10 27 march 10, 2005
ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation pc  stack affected flag(s) to pdf ov z ac c  ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation pc  stack acc  x affected flag(s) to pdf ov z ac c  reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation pc  stack emi  1 affected flag(s) to pdf ov z ac c  rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1)  [m].i; [m].i:bit i of the data memory (i=0~6) [m].0  [m].7 affected flag(s) to pdf ov z ac c  rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1)  [m].i; [m].i:bit i of the data memory (i=0~6) acc.0  [m].7 affected flag(s) to pdf ov z ac c  ht36b2 rev. 1.10 28 march 10, 2005
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1)  [m].i; [m].i:bit i of the data memory (i=0~6) [m].0  c c  [m].7 affected flag(s) to pdf ov z ac c   rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1)  [m].i; [m].i:bit i of the data memory (i=0~6) acc.0  c c  [m].7 affected flag(s) to pdf ov z ac c   rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i  [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7  [m].0 affected flag(s) to pdf ov z ac c  rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i)  [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7  [m].0 affected flag(s) to pdf ov z ac c  rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i  [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7  c c  [m].0 affected flag(s) to pdf ov z ac c   ht36b2 rev. 1.10 29 march 10, 2005
rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i  [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7  c c  [m].0 affected flag(s) to pdf ov z ac c   sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc  acc+[m ]+c affected flag(s) to pdf ov z ac c  sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m]  acc+[m ]+c affected flag(s) to pdf ov z ac c  sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]  1)=0, [m]  ([m]  1) affected flag(s) to pdf ov z ac c  sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]  1)=0, acc  ([m]  1) affected flag(s) to pdf ov z ac c  ht36b2 rev. 1.10 30 march 10, 2005
set [m] set data memory description each bit of the specified data memory is set to 1. operation [m]  ffh affected flag(s) to pdf ov z ac c  set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i  1 affected flag(s) to pdf ov z ac c  siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m]  ([m]+1) affected flag(s) to pdf ov z ac c  siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc  ([m]+1) affected flag(s) to pdf ov z ac c  snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i  0 affected flag(s) to pdf ov z ac c  ht36b2 rev. 1.10 31 march 10, 2005
sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc  acc+[m ]+1 affected flag(s) to pdf ov z ac c  subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m]  acc+[m ]+1 affected flag(s) to pdf ov z ac c  sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc  acc+x +1 affected flag(s) to pdf ov z ac c  swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0  [m].7~[m].4 affected flag(s) to pdf ov z ac c  swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0  [m].7~[m].4 acc.7~acc.4  [m].3~[m].0 affected flag(s) to pdf ov z ac c  ht36b2 rev. 1.10 32 march 10, 2005
sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c  sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c  sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c  tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m]  rom code (low byte) tblh  rom code (high byte) affected flag(s) to pdf ov z ac c  tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m]  rom code (low byte) tblh  rom code (high byte) affected flag(s) to pdf ov z ac c  ht36b2 rev. 1.10 33 march 10, 2005
xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc  acc  xor  [m] affected flag(s) to pdf ov z ac c    xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m]  acc  xor  [m] affected flag(s) to pdf ov z ac c    xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc  acc  xor  x affected flag(s) to pdf ov z ac c    ht36b2 rev. 1.10 34 march 10, 2005
package information 28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394  419 b 290  300 c14  20 c
697  713 d92  104 e  50  f4  g32  38 h4  12  0  10  ht36b2 rev. 1.10 35 march 10, 2005
  +    ! 2  h  &  #
56-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395  420 b 291  299 c8  12 c
720  730 d89  99 e  25  f4  10 g25  35 h4  12  0  8  ht36b2 rev. 1.10 36 march 10, 2005  
-
   ! 2  h &  # 
product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330  1 b reel inner diameter 62  1.5 c spindle hole diameter 13+0.5  0.2 d key slit width 2  0.5 t1 space between flange 24.8+0.3  0.2 t2 reel thickness 30.2  0.2 ht36b2 rev. 1.10 37 march 10, 2005    * *
!
carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24  0.3 p cavity pitch 12  0.1 e perforation position 1.75  0.1 f cavity to perforation (width direction) 11.5  0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4  0.1 p1 cavity to perforation (length direction) 2  0.1 a0 cavity length 10.85  0.1 b0 cavity width 18.34  0.1 k0 cavity depth 2.97  0.1 t carrier tape thickness 0.35  0.01 c cover tape width 21.3 ht36b2 rev. 1.10 38 march 10, 2005  ! a    ! # 2       
ht36b2 rev. 1.10 39 march 10, 2005 copyright  2005 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek
s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 0755-8616-9908, 8616-9308 fax: 0755-8616-9533 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 028-6653-6590 fax: 028-6653-6591 holmate semiconductor, inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com


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